1. Field of the Invention
The present specification relates to a magnetic tunnel junction device and its fabricating method.
2. Description of the Related Art
MRAM (Magnetic Random Access memory) is a non-volatile magnetic random access memory, which has the advantages of high speed access similar as static random access memory (SRAM), small cell size for high density integration similar as dynamic random access memory, and almost infinite writing cycles, which has attracted much attention nowadays.
Recent MRAM realizes its storage function based on the magnetic tunnel junction (MTJ) structure and electron spin polarization effect. Thus, research on MTJ has been greatly advanced. Furthermore, MTJ has found its important application in sensors.
FIGS. 1 to 5 illustrate a typical fabrication flow of MTJ. The structure shown in FIG. 1 and semiconductor device 100A comprises an underlying layer 103 which represents a completed semiconductor device (herein, only part of the device is shown), a first dielectric layer 100 located on the underlying layer 103, a tungsten plug embedded in the first dielectric layer 100 and in contact with the underlying layer 103, and a second dielectric layer 102 located on the first dielectric layer 100. As shown in FIG. 2 and semiconductor device 100B, an opening is formed within the second dielectric layer 102, and multiple-layers for MTJ 104 are deposited. As shown in FIG. 2, MTJ 104 comprises a top electrode layer 1041, a first synthetic anti-ferromagnetic material layer (SAF) 1042, a tunnel insulating layer 1043, a second synthetic anti-ferromagnetic material layer (SAF) 1044, an anti-ferromagnetic pinning layer 1045, and a bottom electrode layer 1046. The first SAF 1042 comprises a first free sublayer (ferromagnetic material), a Ru layer and a second free sublayer (ferromagnetic material). Since the first SAF 1042 contains such a tri-layer structure, magnetic flux lines will loop within such tri-layer structure as shown in the figure, reducing magnetic flux leakage therefore. The second SAF 1044 has a similar structure as well. The total thickness of multi-layer MTJ is in the range of 100-200 nanometers (nm), thus each layer is thin and in the range of 1-20 nm. The tunnel dielectric layer 1043 is the thinnest and is in the range of 1-3 nm. Note that, although the second SAF 1044 is pinned by the anti-ferromagnetic pinning layer 1045 beneath, in some practical applications, however, it is not necessary to pin the second SAF 1044, and thus the anti-ferromagnetic pinning layer 1045 can be omitted. Further, although magnetic flux lines looping toward the same direction is shown in the figure, it is merely an example, and the loop direction of magnetic flux lines in the first synthetic anti-ferromagnetic material layer (SAF) 1042 can be reversed to represent the storage of 1 or 0.
FIG. 2 shows an optimized MTJ structure. After FIG. 2, then, the stack of multi-layers of MTJ 104 are patterned with a mask and dry etching, so that merely a portion of the MTJ layers 104 is located on the contact 101 as shown in FIG. 3 via semiconductor device 100C. In traditional conventional MTJ processes, etching methods such as FIB or plasma etching or the like are adopted so that various materials in the stack of multiple layers 104 can be etched by the same etching process for process simplicity and achieving minimum MTJ pattern. Next, as shown in FIG. 4 and semiconductor device 100D, a dielectric layer 105 is deposited and planarized (by chemical-mechanical planarization, or CMP) to fill up that open. Then, an electric contact is formed with tungsten plug to connect electrically to the MTJ 104. Then, as in FIG. 5 and semiconductor device 100E, a metal interconnect layer 106 is formed on the second dielectric layer 102 to electrically connect the MTJ 104 through the contact.
It is well known in the art that the above-identified layers are deposited in vacuum with thickness of 1-10 nm of each layer. The deposition is preferable to be conducted sequentially, without breaking the vacuum of process chamber, so as to avoid contamination during the deposition. One deposition for all the multiple layers and followed by etching process may prevent the contamination to the most extent.
On the other hand, as well known in the art, the tunnel insulating layer 1043 has a thickness of about 1-3 nm. When the layer 1043 is exposed to etching plasma and etched as shown in FIG. 3, its edge of the tunnel dielectric layer 1043 is easily damaged. Damaged edge of tunnel insulating layer 1043 may cause high leakage current, breakdown of the insulating layer 1043, and error rate of stored data, as a result, it leads to low yield rate and high manufacturing cost. In summary, all of above may increase MTJ manufacturing cost.
On the other hand, in practice, there are many sophisticated manufacturing lines for CMOS. Hence, it is desirable to fabricate MTJ with CMOS processes.
Besides, with the continuously scaling of semiconductor devices, it is highly desirable to simplify MTJ structures. Therefore, the tri-layer SAF 1042 and the second SAF 1044 of FIG. 2 can be substituted by single layer of ferromagnetic material, with trade-offs of degraded signal intensity due to larger magnetic flux leakage.
In view of above and other aspects, a new technical solution is proposed by the applicants in this present specification.